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DVB IP-Cores

QAM & DUC

Digital upconversion is a consequent step on the way to a completely digital signal processing.
DUC provides a substantially higher signal quality of the different carriers while the output frequency can be chosen freely. This means a compact design of the hardware platform at significantly lower costs.
maintech's QAM & DUC allows a low power consumption respectively high energy efficiency. All channels can be set and switched on/off individually. The solution is adjacent channel compatible. Excellent MER and shoulder attenuation values are key advantages of the multiple FPGA QAM modulation with DUC.

DVB-C Modulation According to ETSI-EN 300429 V1.2.1 with Digital Upconversion

QAM Modulation according to ETSI EN 300 429 V1.2.1
16 DVB-C channels to 7000 kSym/s max
Signal quality: MER > 44dB
Input: MPEG2 transport stream
Output on AD9739 (or similar DAC)
Channels can be chosen freely in a frequency range between 50 and 950 MHz
Output level of each channel can be attenuated individually
Power consumption ca. 1 Watt / channel
TS-Processing, modulators and upconversion settable by SPI (or other interfaces  at your choice)
Apart from configuration no CPU support needed
No dependencies on 3rd-party IP cores or code generators

FPGA Ressource Requirements

Xilinx Virtex 6 / 7
Xilinx Kintex 7
Altera Stratix IV / V
Altera Arria II / V

Leaflet QAM DUC IP-Core.pdf

DVB S/T/C – DVB S2/T2/C2 – QAM&DUC

For custom hardware developments, the use of an IP core offers the chance to save development time and opens the possibility of using existing hardware in new applications.

The maintech IP cores for FPGA modulation are especially suited for this as they were developed with special attention on the following aspects:

  • Flexible configuration depending on available ressources and necessary RF processing
  • Operation with a single 27MHz crystal
  • A powerful interpolation filter makes sure that any desired DAC sample rate can be used
  • The resulting IF can be freely chosen in steps of a few hundred Hertz
  • To compensate for the unavoidable FIFO delay, a stuffing generator and PCR correction is available which raises the transport stream rate to the needed transmission rate
  • All transmission parameters can be changed during operation of the IP core; changes are immediately applied

Licensing

The maintech IP cores are available in different configurations. Depending on your budget and wishes, finished binary images or the complete VHDL source code can be delivered – please contact us for a quote for your planned application.

DVB-S2

DVB-S2, follow-up of the DVB-S standard, features a higher transmission capacity at the same bandwidth and transmission power. Not only SDTV but HDTV and H.264 data streams can be transmitted in that efficient mode, too. DVB-S2 modulation can also make sense for the transmission of great masses of data or internet services.
maintech's IP-Core unites all advantages of the DVB-S2 modulation: The IP-Core provides a powerful LDPC error corection, all constellation types as QPSK, 8PSK, 16APSK, 32APSK and the roll off factors 0.2, 0.25 and 0.35.

DVB-S2 Modulation according to ETSI-EN 302307 V1.2.1

Constellations: QPSK, 8PSK, 16APSK, 32APSK
Symbol rate 1-32 MSym/s
Implementation using a single 27MHz crystal; other frequencies are possible
Integrated IF upconverter and interpolation filter
Level correction
FEC (LDPC): 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10 (depending on the constellation type)
TS processing (stuffing packets generator, PCR correction)
No external dependencies
In conjunction with the AD9772 DAC (I/Q output) or AD9744 DAC (IF output): >27dB MER

FPGA Ressource Requirements

Altera Cyclone 3 (EP3C40), IF output: ~13200 LEs, 70 blockrams, 69 multipliers

Xilinx Spartan 3 (XC3SD1800A), I/Q baseband: ~4400 slices, 30 blockrams, 72 multipliers

Lattice: information on request

Leaflet DVB-S2 IP-Core.pdf

DVB-T2

The transmission capacity of DVB-T2 is 30% and more higher than the capacity of the basic standard DVB-T. DVB-T2 is therefore especially suited for HDTV applications and the transmission of great masses of data.
maintech's IP-Core features a powerful LDPC error correction, the new IFFT Modes and Guard Intervals, Cell and Time Interleaver. All constellation types as QPSK, 16QAM, 64QAM and 256QAM (normal/rotated) are supported.

DVB-T2 Modulation according to ETSI-EN 302 755 V.1.1.1

Constellations: QPSK, 16QAM, 64QAM, 256QAM (normal or rotated)
IFFT Modes: 1k, 2k, 4k, 8k, 16k, 32k (normal or extended)
Bandwidths: 1.7, 5, 6, 7, 8, 10 MHz
Implementation using a single 27MHz crystal; other frequencies are possible
Integrated IF upconverter and interpolation filter
FEC (LDPC): 1/2, 3/5, 2/3, 3/4, 4/5, 5/6
Cell Interleaver incl., Time Interleaver optionally
TS processing (stuffing packets generator, PCR correction)
No external dependencies
In conjunction with the AD9772 DAC (I/Q output) or AD9744 DAC (IF output): >27dB MER

FPGA Ressource Requirements

Altera, Xilinx or Lattice; information on request

Leaflet DVB-T2 IP-Core.pdf

DVB-C2

DVB-C2 is based on COFDM Modulation and features a significantly higher transmission capacity than the DVB-C standard of the first DVB generation. DVB-C2 is therefore suited for HDTV as well as for the transmission of great masses of data.

maintech's IP-Core features the LDPC error correction as well as Bit, Frequency und Time interleaver (optionally), freely selectable bandwidth and – depending on the DAC – an MER >40dB. All constellation types as QPSK, 16QAM, 64QAM, 256QAM, 1024QAM, 4096QAM are supported.

DVB-C2 Modulation according to ETSI-EN 302 769 V1.2.1

Constellations: QPSK, 16QAM, 64QAM, 256QAM, 1024QAM, 4096QAM
FEC (LDPC): 2/3, 3/4, 4/5, 5/6, 8/9, 9/10
Frequency Interleaver incl., Time Interleaver optionally
Number of dataslices: only limited by FPGA size
Bandwidth: freely selectable, only limited by FPGA size
Channel spacing: 6, 8 MHz
TS processing (stuffing packets generator, PCR correction)
Output: Baseband, IF or target frequency (optionally)
MER >40dB (depending on the DAC)
Implementation using a single crystal
No external dependencies

FPGA Ressource Requirements

Altera, Xilinx or Lattice; information on request

Leaflet DVB-C2 IP-Core.pdf

DVB-S

DVB-S Modulation according to ETSI-EN 300421 V1.1.2

If required, also available: The DVB-S IP-Core. Please ask for a quotation with the relevant specifications.

FPGA Ressource Requirements

Altera, Xilinx or Lattice: Information on request

DVB-T

DVB-T procides a powerful forward error correction scheme. The transmission is based on the standardised ISO/IEC13818-1 MPEG2 transport stream which specifies the multiplexing of audio, video and management data in packets of 188 bytes size.

The error correction algorithms can be configured to match the working environment perfectly – the resulting datarates are in the range between 4.9MBit/s and 31.6MBit/s at a RF bandwidth of 8MHz. Non-standardised datarates and bandwidths are possible.

DVB-T Modulation according to ETSI-EN 300744 V1.5.1

Constellations: QPSK, QAM16, QAM64
FEC: 1/2, 2/3, 3/4, 5/6, 7/8
Guard Intervals: 1/4, 1/8, 1/16, 1/32
IFFT Modes: 2k and 8k
Bandwidth: 6MHz, 7MHz and 8MHz
Implementation using a single 27MHz crystal
Integrated IF upconverter and interpolation filter
IF output adjustable between 3.5MHz and 70MHz
Level correction down to -10dB
TS processing (bitrate adaption, PCR correction)
No external dependencies
In conjunction with the AD9772 DAC: >40dB MER

FPGA Ressource Requirements

Altera Cyclone 3 (EP3C55), 2k/8k-Mode, IF output: ~10500 LEs, 87 blockrams, 21 multipliers

Xilinx Spartan 3 (XC3S400), 2k-Mode, I/Q baseband: ~3000 slices, 12 blockrams, 16 multipliers

Lattice ECP3 (LFE3-70E), 2k/8k-Mode, IF output: ~7400 slices, 44 blockrams, 31 multipliers

Leaflet DVB-T IP-Core.pdf

DVB-C

DVB-C Modulation according to ETSI-EN 300429 V1.2.1

Constellations: QAM16, QAM32, QAM64, QAM128, QAM256
Symbol rate 1000-7000 ksym/s
MER >40dB
Level correction down to -10dB
TS Input 8 Bit parallel + clock & sync (SPI), PCR correction included
Platforms: Altera and Xilinx
IF Output: I/Q baseband or continuous between 3.5MHz and 70MHz

FPGA Ressource Requirements

Altera Cyclone 3 (EP3C55), IF output: ~6000 LEs, 9 blockrams, 33 multipliers

Xilinx Spartan 3 (XC3S400), I/Q baseband: ~1700 slices, 1 blockram, 16 multipliers

Leaflet DVB-C IP-Core. pdf

ATSC

ATSC Modulation according to A/53-2 (17.07.1999)

We also offer an IP-Core for an ATSC modulator – please contact us to be informed about the relevant parameters.

FPGA Ressource Requirements

Altera, Xilinx or Lattice: Information on request

maintech GmbH | Max-Planck-Straße 8 | D-97204 Höchberg | Tel. +49-(0)931-4070690 | info@maintech.de |
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